The need for high speed wireless and optical links is increasing every day and one of the bottle necks is the availability of high speed analog to digital converters (ADCs). These ADCs form the front end of almost every digital system. Several fields from defense to communication to aviation can all benefit from a faster ADC. Moreover, with the rise of wide-bandwidth pulse-based systems, a wide-bandwidth ADC is desirable for an impulse receiver. Over the course of time, ADCs have evolved and many different topologies have been adapted from sample and hold to track and hold to master-slave configuration and many more, all with the objective to improve the performance. Furthermore, to get a superior performance figure, designers have often focused on using expensive InP or GaAs fabrication processes.
A time domain wide-bandwidth pulse based system architecture mitigates/eliminates some of the inherent drawbacks of narrow-band continuous wave (CW) systems. Such systems may utilize time domain pulses for communication and localization. Being a pulse based architecture, the system is ultra wide-band and uses a single pulse for each transmitted symbol. Moreover, the ability to coherently combine the pulses at specific point adds a layer of spatial encryption and power combining, which is difficult in CW architecture.
Analog to digital converters (ADCs) converts the continuous physical quantity to digital bits that represents its amplitude. The conversion involves quantization of parameters thus introducing some error. In order to make an on-chip wide-bandwidth pulse based communication and localization systems, it is very important to have an ultra wide-band high-speed ADC core around which receivers can be built.
ADCs:
ADCs may use sample & hold techniques in which the input signal is captured and the value is held for a specific period of time, acting as temporary memory devices. An exemplary sample & hold circuit may comprise a charge storing element like capacitor, a fast transmission switch and a high input impedance amplifier. As shown in FIG. 1, a capacitor 10 is connected to the input via switch (S1) 20. When this switch 20 is closed, the voltage across the capacitor 10 is proportional to the average voltage applied during the “ON” time and duration of “ON” time. Knowing the duration of “ON” time, the average voltage across the capacitor can be calculated and hence sample the input signal. This architecture works very well for lower frequency spectrum and low sampling rate. However, as we increase the input frequency, many technical challenges arises.
Switch Isolation:
While implementing a switch in CMOS, a transmission gate may be utilized, such as an exemplary transmission gate shown in FIG. 2. This transmission gate is composed of a P-MOS 210 and N-MOS 220 in parallel (FIG. 2) which is fed by a clock′ (Ā) and clock (A). Ideally, the transmission should provide infinite impedance when switched “OFF”, which is generally true for lower frequencies. However, as we increase the frequency, the isolation decreases as shown in the frequency response (FIG. 3) of a transmission gate in 45 nm technology (both transistor are in “Off” state). This phenomenon can be explained with the fact that the source(S) drain(D) parasitic capacitor (CSD) provides an alternate path for the signal to pass as shown in FIG. 2. This alternate path provides considerable about of coupling at high frequencies and reduces the isolation.
Limitation of Sampling Window:
Sampling window in an ADC is defined as the window during which the sampling of the signal is taking place, as illustrated in FIG. 4. For example, suppose a sample of the signal at point “X” is desired. The switch-1 starts to switch on at t=0 and completely switches on after t=trise. The switch remains on for duration tduration and then starts to switch off with the closing time of tfall. Assuming that trise and tfall are comparably smaller than tduration, then the voltage across the capacitor is proportional to the mean of the time-varying input signal. When tduration is long, the input signal can vary and cause a large error on the sampling voltage. To minimize this error, tduration is preferably small. This means the switch and the holding capacitors should be very small. However, when the holding capacitor is small, the leakage current during the “OFF” can easily change the voltage on the holding capacitor and cause a large error, which is discussed further below.
Leakage Current During “OFF” State:
After the sampling is done, the switch-1 is closed and the voltage across the capacitor is read by a high impedance amplifier, but this process is usually much longer than tduration and the leakage current caused by the switch can change the voltage during the “OFF” stage and increase the error. For example, as shown in FIG. 5, voltage output (Vo) from a transmission gate may be non-zero due to incomplete isolation and leakage current.
In new architecture discussed herein, a new concept is provided in which the accuracy of sampling window of ADC can be increased, by providing active cancellation in the transmission gate. This active-cancellation eliminates the leakage current from the input when the switch is OFF, thus increasing isolation even at higher frequencies.
Further, a broadband time-domain pulse-based directional antenna modulation architecture is also disclosed herein. The architecture may utilize multiple transmitters synchronized at the symbol level to generate a narrow information beamwidth.